Techniques for biasing a radio frequency digital to analog converter

ABSTRACT

Various techniques for biasing a radio frequency digital-to-analog converter are described. In one embodiment, a baseband processor may comprise a plurality of output drivers to generate a plurality of base currents for biasing a radio frequency digital-to-analog converter. The baseband processor may comprise a serial control interface to generate a programming signal for controlling a relationship among the plurality of base currents. Other embodiments are described and claimed.

RELATED APPLICATIONS

This application is related to commonly assigned U.S. patent applicationSer. No. 11/398,060 titled “Baseband Signal Processor” and U.S. patentapplication Ser. No. 11/398,286 titled “Differential Analog Filter”filed on Apr. 4, 2006. These applications are incorporated by reference.

BACKGROUND

A mobile telecommunications transmitter, such as a polar transmitter,may include a polar digital radio frequency power amplifier (RF PA) toamplify a signal prior to transmission. In a polar transmitter, the datato be transmitted is separated into amplitude and phase signals. Afterseparation, the phase signal is applied to a phase modulator, and theamplitude signal is applied to an amplitude modulator, such as a radiofrequency digital-to-analog converter (RFDAC).

In operation, the RFDAC may be used to modulate the amplitude signal aswell as to control the power that is transmitted. Accordingly, there maybe a need for systems and techniques for biasing an RFDAC to improvepower control and to optimize RF PA power efficiency over a range ofoutput power.

SUMMARY

In one embodiment, a baseband processor may comprise a plurality ofoutput drivers to generate a plurality of base currents for biasing aradio frequency digital-to-analog converter. The baseband processor maycomprise a serial control interface to generate a programming signal forcontrolling a relationship among the plurality of base currents.

In one embodiment, a baseband processor may comprise a plurality ofoutput drivers to generate a plurality of base currents for biasing aradio frequency digital-to-analog converter. The plurality of outputdrivers may receive a single power level signal to adjust the pluralityof base currents.

In one embodiment, a radio frequency digital-to-analog converter maycomprise a plurality of gain stages to be biased by a plurality of basecurrents. The plurality of base currents may be generated by a basebandprocessor based on a single power level signal.

In one embodiment, a baseband signal processing method may comprisegenerating a programming signal for controlling a relationship among aplurality of base currents and biasing a radio frequencydigital-to-analog converter with the plurality of base currents toimprove power efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one embodiment of a baseband signal processingsystem.

FIG. 2 illustrates one embodiment of a tuning voltage generation system.

FIG. 3 illustrates one embodiment of output driver system.

FIG. 4 illustrates one embodiment of an RFDAC.

DETAILED DESCRIPTION

FIG. 1 illustrates one embodiment of a baseband signal processing system100. As shown, the baseband signal processing system 100 may comprise anRFDAC 110 to be biased by a baseband processor 120. The RFDAC 110 may beimplemented, for example, by an RF PA. In various implementations, thebaseband processor 120 may be arranged to generate a plurality of basecurrents including for example, base current I_(B1), base currentI_(B2), and base currents I_(b1)-I_(bn) for biasing the RFDAC 110.

As shown, the RFDAC 110 may comprises a plurality of gain stagesincluding, for example, a first gain stage 111, a second gain stage 112,and a third gain stage 113 which may be AC coupled together for thecarrier and phase input from the output of the second stage. In thisembodiment, an RF signal Φ is input to the first gain stage 111 of theRFDAC 110, and the base current I_(B1) is applied from the basebandprocessor 120 to the first gain stage 111 of the RFDAC 110. As such, thefirst gain stage 111 is biased by the base current I_(B1) and to amplifyRF signal Φ.

In the RFDAC 110, the base current I_(B2) is applied from the basebandprocessor 120 to the second gain stage 112. As such, the second gainstage 112 is biased by the base current I_(B2) and to further amplify RFsignal Φ provided from the first gain stage 111. In general, the basecurrent I_(B1) and the base current I_(B2) will be different because thesecond stage 112 input power is amplified by the first gain stage 111.Therefore, the second gain stage 112 is biased at a higher DC outputpoint.

After being amplified by the first gain stage 111 and the second gainstage 112, the amplified RF signal Φ is sent to the third gain stage113. In the third gain stage 113, the amplified RF signal Φ is modulatedby a baseband signal and is then transmitted through the antenna 114. Inthis embodiment, the baseband signal may comprise an amplitude signalprovided to the third gain stage 113 through the base currentsI_(b1)-I_(bn). In various implementations, the combined base currentsI_(b1)-I_(bn) provided from the baseband processor 120 may be used tocontrol the amplification of the RF signal Φ provided by the third gainstage 113.

In various embodiments, the baseband processor 120 may be arranged toadjust the base currents I_(B1), I_(B2), and I_(b1)-I_(bn) toindividually bias the first gain stage 111, the second gain stage 112,and the third gain stage 113 of the RFDAC 110. Since the RFDAC 110comprises three gain stages, it may be necessary to adjust the bias foreach of the gain stages individually to obtain optimal power efficiencyand linearity. This may be necessary, for example, to compensate for andto minimize the effects of variations in on-chip and off-chip deviceparameters, such as CMOS process variations, power supply variations,temperature variations, transconductance (G_(m)) variations, and soforth. In many cases, the relationship or ratio required among the basecurrents applied to each gain stage of the RFDAC 110 may not be the samefrom chip to chip.

As shown, the RFDAC 110 may comprise a sense device 115. In variousembodiments, the gain stages of the RFDAC 110 may comprise transistorsimplemented as hetero-junction bipolar transistor (HBT) devices (e.g.,GaAs HBT devices). In such embodiments, the sense device 115 maycomprise an HBT device formed integrally on the same substrate as theother transistors of the RFDAC 110 so that the variations due to processvariables for the other transistors of the RFDAC 110 and the sensedevice 115 are similar.

In various implementations, the baseband processor 120 may be arrangedto detect the ratio of the collector-emitter current to the base-emittercurrent, or current gain (β), of the sense device 115. From the detectedβ of the sense device 115, the baseband processor 120 may generate acompensation signal that is proportional to 1/β. In various embodiments,the 1/β compensation signal may be used by the baseband processor 120 togenerate the base currents I_(B1), I_(B2), and I_(b1)-I_(bn).

In one embodiment, the baseband processor 120 may output a current MV_Bto the base of the sense device 115 (e.g., HBT device) and may provide afixed precision current MV_C to the collector of the sense device 115 todetermine the β of the sense device 115. The baseband processor 120 mayautomatically adjust the current MV_B by sensing and maintaining thevoltage at the collector of the sense device 115 such that the collectorvoltage will be high enough to maintain the sense device 115 in itslinear operating range. When such condition is achieved, through theadjustment of the current MV_B, the resulting current MV_B is 1/β of thecurrent MV_C.

In various embodiments, the baseband processor 120 may be implemented byan analog baseband signal processor and/or an amplitude basebandprocessing chip, for example. As shown, the baseband processor 120 mayinclude a power control portion 130, a filter portion 140, and a driverportion 150. The power control portion 130, the filter portion 140, andthe driver portion 150 are described in further detail below as well asin commonly assigned U.S. patent application Ser. No. 11/398,060 titled“Baseband Signal Processor” and U.S. patent application Ser. No.11/398,286 titled “Differential Analog Filter,” which are incorporatedby reference.

The power control portion 130 may comprise a serial control interface131. The serial control interface 131 may be arranged to provide acommunication link from a computer, such as a personal computer (PC) tothe baseband processor 120. In various implementations, the serialcontrol interface 131 may provide a user with the ability to accessand/or program various elements within the baseband processor 120. Forexample, the serial control interface 121 may enable programming ofelements within the driver portion 150.

In one embodiment, the serial control interface 131 may be arranged togenerate a programming signal for controlling the set of base currentsI_(B1), I_(B2), and I_(b1)-I_(bn) provided to the RFDAC 110. Forexample, the serial control interface 131 may allow a user to send aprogramming signal to the driver portion 150 of the RFDAC 110 forindividually adjusting the base currents I_(B1), I_(B2), andI_(b1)-I_(bn).

In various implementations, the serial control interface 131 may enablea user to maintain a fixed ratio among the output base currents I_(B1),I_(B2), and I_(b1)-I_(bn). The ratio among the base current I_(B1), thebase current I_(B2), and the base currents I_(b1)-I_(bn) may becontrolled, for example, to improve and/or optimize RF PA powerefficiency. As such, RF PA power efficiency may be maintained over abroad range of output power. In some embodiments, further improvementand/or optimization may be achieved by additional individual fine-tuningof the base currents I_(B1), I_(B2), and I_(b1)-I_(bn).

In various embodiments, the serial control interface 131 may be used toadjust G_(m) values of the driver portion 150 for biasing individualstages of the RFDAC 110. The G_(m) values of the driver portion 150 maybe adjusted to control the base currents I_(B1), I_(B2), andI_(b1)-I_(bn) in order to improve and/or optimize RF PA efficiency. Invarious implementations, once the optimal biasing conditions and/orG_(m) values are determined, the setting may be latched into the memoryof the serial control interface 131.

In various embodiments, the baseband processor 120 may be arranged toprovide unified or “single point” power control for establishing theoutput power of an RF PA. In one embodiment, for example, the basebandprocessor 120 may be arranged to use a single power level signal toadjust the base currents I_(B1), I_(B2), and I_(b1)-I_(bn) for all threestages of the RFDAC 110 simultaneously. In various implementations, thepower level signal may comprise a single power control voltage appliedthrough the filter portion 140 to the driver portion 150 creating acentral or “one knob” control point.

Referring to the embodiment of FIG. 1, for example, the “one knob”control signal may refer to the input signal “POWER LEVEL SIGNAL.” Inthis embodiment, two sets of power control signals may be generated fromthis input signal. The first set of power control signals may includesignals that are DC in nature but proportional to the input POWER LEVELSIGNAL. The first set of power control signals may be applied to thedriver portion 150 for the first gain stage 111 and the second gainstage 112 of the RFDAC 110.

The second set of power control signals may comprise n (e.g., n=11)analog signals swinging between two levels and having amplitudeproportional to the input POWER LEVEL SIGNAL. In this embodiment, thesource of these n analog signals may comprise n 1-bit DACs or analogmultiplexers structured and arranged so that their analog outputs areproportional to the POWER LEVEL SIGNAL. Tracing back a step further, thesource of the n analog signals may comprise n digital “AMPLITUDESIGNALS” as shown in FIG. 1.

In various embodiments, when this central power control signal isvaried, all output currents, I_(B1), I_(B2) and I_(b1) . . . I_(bn) willchange simultaneously proportional to constants G_(m1), G_(m2), andG_(m3) respectively giving the effect of “one knob” control to theoutput power at RFDAC 110. The proportionality constants G_(m1), G_(m2),and G_(m3), may be individually programmable through the serial controlinterface 131 and registers residing there. When applied to the driverportion 150, the single power control voltage may bias multiple stage ofthe RFDAC 110 simultaneously based on the G_(m) values and establish theoutput power of the RF PA.

The baseband processor 120 may be arranged to receive inputs including,for example, amplitude signals and the power level signal. In somecases, the inputs to the baseband processor 120 may be received from adigital signal processor and/or baseband integrated circuit implementinga coordinate rotation digital computer (CORDIC) algorithm.

In various implementations, the baseband processor 120 may receive inputdata separated into amplitude and phase signals. For example, the RFDAC110 may be used to modulate an input in-phase/quad-phase (IQ) basebandsignal. Before the IQ baseband signal is applied to the RFDAC 110, it isfirst divided into amplitude and phase signals. The amplitude signalsmay be quantized by the baseband processor 120 and output to the RFDAC110, whose RF input is separately modulated by the phase component. Insome embodiments, the RFDCA 110 may comprise the last stage of a polartransmitter, making it possible to reduce current drain quickly as thetransmit power level is reduced.

As shown, the power control portion 130 may include one or more analogmultiplexer and level shift modules 132-1-x, where x represents anypositive integer value. In various implementations, the analogmultiplexer and level shift modules 132-1-x may be arranged to receiveamplitude signals and the power level signal. The amplitude signals maycomprise, for example, one or more digital amplitude baseband signals.In one embodiment the amplitude signal may comprise an n-bit (e.g.,11-bit) coded digital amplitude signal.

The analog multiplexer and level shift modules 132-1-x may be arrangedto convert the n-bit coded digital amplitude signal to analog. Invarious embodiments, the analog multiplexer and level shift blocks132-1-x may perform digital-to-analog conversion (DAC) according to theinput power level resulting in amplitude scaled to the power level. Forexample, a code of 1 input to the analog multiplexer and level shiftmodules 132-1-x may be converted to 200 mV, referenced to a common modeDC level, according to the power level.

The baseband processor 120 may comprise a filter portion 140 including aplurality of filters such as a first filter 141 and a bank of filters142-1-y, where y represents any positive integer value. In variousembodiments, the first filter 141 and the bank of filters 142-1-y may bearranged in parallel to filter the output from the analog multiplexerand level shift modules 132-1-x.

The filter portion 140 may employ various types of filters, such aslow-pass filters (LPFs) having a predetermined cut-off frequency. Insome cases, each LPF may be implemented as a linear filter, such as aBessel filter with maximally flat group delay (linear phase response)and small overshoot. For example, the LPFs may be implemented asthird-order Bessel filters. In low power consumption embodiments, thefilter portion 140 may employ a Sallen-Key architecture cascaded by apassive RC network. The embodiments are not limited in this context.

The baseband processor 120 may comprise a driver portion 150 including aplurality of tuning voltage (V_(tune)) generators such as a V_(tune1)generator 151, a V_(tune2) generator 152, and a V_(tune3) generator 153.While three Vine generators are shown by way of example, it can beappreciated that a greater or fewer number of V_(tune) generators may beused in other implementations. In one embodiment, the V_(tune1)generator may generate a tuning voltage V_(tune1), the V_(tune2)generator may generate a tuning voltage V_(tune2), and the V_(tune3)generator may generate a tuning voltage V_(tune3). As shown, the tuningvoltage V_(tune3) may be amplified or buffered by an amplifier 154, suchas a unity-gain amplifier.

In various implementations, the V_(tune) generators may be independentlycontrolled by the serial control interface 131. Each of the V_(tune)generators may comprise, for example, a current multiplier (I-multiplieror current-multiplying-DAC) configured to be independently programmed bythe serial control interface 131. By independently controlling each ofthe V_(tune) generators, the serial control interface 131 may bearranged to control the ratio of the base currents I_(B1), I_(B2), andI_(b1)-I_(bn) provided to each stage of the RFDAC 110.

In one embodiment, the V_(tune1) generator 151, the V_(tune2) generator152, and the V_(tune3) generator 153 each may comprise a 5-bitprogrammable I-multiplier, and the serial control interface 131 maygenerate a 15-bit programming signal. The 15-bit programming signal fromthe serial control interface 131 may be divided into three 5-bit groups,with each 5-bit group independently programming a separate I-multiplier.Using the 5-bits from the serial control interface 131, themultiplication factor for each I-multiplier of the V_(tune1) generator151, the V_(tune2) generator 152, and the V_(tune3) generator 153 may beprogrammed.

In various embodiments, the tuning voltages V_(tune1), V_(tune2), andV_(tune3) may be different but proportional with respect to the valuesof the three 5-bit digital values, respectively. In one embodiment, theV_(tune) generators may be arranged to generate tuning voltagesV_(tune1), V_(tune2), and V_(tune3) in proportion of 1:2:3 with respectto each other. For example, the V_(tune1) generator may comprise anI-multiplier programmed with a multiplication factor (K₁) equal to one,the V_(tune2) generator may comprise an I-multiplier programmed with amultiplication factor (K₂) equal to two, and the V_(tune3) generator maycomprise an I-multiplier programmed with a multiplication factor (K₃)equal to three. After being programmed, the I-multipliers of theV_(tune) generators may be arranged to multiply a current I_(D)individually by K₁, K₂, and K₃ to generate currents I_(D1), I_(D2), andI_(D3), which are used to generate the tuning voltages V_(tune1),V_(tune2), and V_(tune3).

As shown, the driver portion 150 may comprise a plurality of outputdrivers including a G_(m1) driver 155, a G_(m2) driver 156, and G_(m3)drivers 157-1-n, where n represents any positive integer value. Invarious embodiments, the tuning voltages V_(tune1), V_(tune2), andV_(tune3) may be provided to the output drivers including the G_(m1)driver 155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-n.Collectively, the tuning voltages V_(tune1), V_(tune2), and V_(tune3)may be used to adjust and control the G_(m) value of each of the outputdrivers to provide optimized RF PA power efficiency over a range ofoutput power.

In one embodiment, the tuning voltage V_(tune1) may be provided to theG_(m1) driver 155, the tuning voltage V_(tune2) may be provided to theG_(m2) driver 156, and the tuning voltage V_(tune3) may be provided tothe G_(m3) drivers 157-1-n. Each of the G_(m1) driver 155, the G driver156, and the G_(m3) drivers 157-1-n may comprise, for example, amultiplier for multiplying the tuning voltages V_(tune1), V_(tune2), andV_(tune3). In various implementations, the values G_(m1), G_(m2), andG_(m3) may be adjusted to provide a constant ratio among the G_(m1)driver 155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-n. Byadjusting the values G_(m1), G_(m2), and G_(m3) the amount by which thebase currents I_(B1), I_(B2), and I_(b1)-I_(bn) are adjusted may becontrolled. For example, the ratio among the base current I_(B1)provided by the G_(m1) driver 155, the base current I_(B2) provided bythe G_(m2) driver 156, and the base currents I_(b1)-I_(n) provided bythe G_(m3) drivers 157-1-n may be controlled to allow optimization of RFPA power efficiency in the RFDAC 110.

In various embodiments, the G_(m1) driver 155, the G_(m2) driver 156,and the G_(m3) drivers 157-1-n may be arranged to use a single powerlevel signal to simultaneously adjust the base currents I_(B1), I_(B2),and I_(b1)-I_(bn). In such embodiments, the power level may be filteredby the first filter 141 and sent to the G_(m1) driver 155 and to theG_(m2) driver 156. The power level also may be filtered by the bank offilters 142-1-n and sent to the G_(m3) drivers 157-1-n. The power levelmay comprise, for example, a single power control voltage applied to theG_(m1) driver 155, the G_(m2) driver 156, and the G_(m3) drivers157-1-n.

In various implementations, all of the output drivers including theG_(m1) driver 155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-nmay be adjusted by a certain amount according to the power level. Assuch, a single power level signal may be used to bias multiple stage ofthe RFDAC 110 simultaneously based on the G_(m) values. In variousimplementations, the power level signal may comprise a single powercontrol voltage applied to the driver portion 150 creating a central or“one knob” control point. In such implementations, unified or “singlepoint” power control is provided for establishing the output power of anRF PA.

Referring to the embodiment of FIG. 1, for example, the “one knob”control signal may refer to the input POWER LEVEL SIGNAL. In thisembodiment, two sets of power control signals are generated from thePOWER LEVEL SIGNAL. The first set of power control signals includessignals that are DC in nature but proportional to the input POWER LEVELSIGNAL. The first set of power control signals are applied to the G_(m1)driver 155 and the G_(m2) driver 156 for the first gain stage 111 andthe second gain stage 112 of the RFDAC 110.

The second set of power control signals may comprise n (e.g., n=11)analog signals swinging between two levels and having amplitudeproportional to the input POWER LEVEL SIGNAL. In this embodiment, thesource of these n analog signals may comprise 1-bit DACs, such as analogmultiplexer and level shift blocks 132-1-x shown in FIG. 1. The analogmultiplexer and level shift blocks 132-1-x may be structured andarranged so that their analog outputs are proportional to the POWERLEVEL SIGNAL. Tracing back a step further, the source of the n analogsignals may comprise n digital AMPLITUDE SIGNALS as shown in FIG. 1.

In this embodiment, when the central power control signal is varied, alloutput currents, I_(B1), I_(B2) and I_(b1) . . . I_(bn) will changesimultaneously proportional to the constants G_(m1), G_(m2), and G_(m3)respectively giving the effect of “one knob” control to the output powerat RFDAC 110. The proportionality constants G_(m1), G_(m2), and G_(m3)are individually programmable through the serial control interface 131and registers residing there. When applied to the G_(m1) driver 155, theG_(m2) driver 156, and the G_(m3) drivers 157-1-n, the single powercontrol voltage may bias multiple stage of the RFDAC 110 simultaneouslybased on the G_(m) values and establish the output power of the RF PA.

In various embodiments, the output drivers including the G_(m1) driver155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-n may be biasedto compensate for variations in on-chip and off-chip device parameters,such as CMOS process variations, power supply variations, temperaturevariations, G_(m) variations, and so forth.

As shown, the driver portion 150 may comprise a 1/β generator 158. Invarious implementations, the 1/β generator 158 may be arranged to detectthe β of the sense device 115 of the RFDAC 110. From the detected β ofthe sense device 115, the 1/β generator 158 may generate a compensationsignal that is proportional to 1/β.

In various embodiments, the output drivers including the G_(m1) driver155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-n may generatebase currents I_(B1), I_(B2), and I_(b1)-I_(bn) based on the signalproportional to 1/β. In one embodiment, for example, the 1/β generator158 may provide the 1/β compensation signal to the V_(tune1) generator151, the V_(tune2) generator 152, and the V_(tune3) generator 153. Whenbiased by the tuning voltages V_(tune1), V_(tune2), and V_(tune3), theG_(m1) driver 155, the G_(m2) driver 156, and the G_(m3) drivers 157-1-nmay be arranged to generate base currents I_(B1), I_(B2), andI_(b1)-I_(bn) which are compensated for β variation in the RFDAC 110.Base currents (e.g., I_(B1), I_(B2), and I_(b1)-I_(bn)) carrying thecharacteristic of 1/β may be multiplied by β so that the collectorcurrents of devices in the RFDAC 110 are substantially independent ofvariations in β.

FIG. 2 illustrates one embodiment of a tuning voltage generation system200. In various embodiments, the tuning voltage generation system 200may be implemented by the baseband processor 120 depicted in FIG. 1. Theembodiments, however, are not limited in this context.

As shown, the tuning voltage generation system 200 comprises a serialcontrol interface 210, a 1/β generator 220, and a plurality of Vinegenerators including a V_(tune1) generator 230, a V_(tune2) generator240, and a V_(tune3) generator 250. A common supply voltage V_(DD)(e.g., 2.85V) is applied to the 1/β generator 220, the V_(tune1)generator 230, the V_(tune2) generator 240, and the V_(tune3) generator250. While three Vine generators are shown by way of example, it can beappreciated that a greater or fewer number of V_(tune) generators may beused in other implementations.

The 1/1 generator 220 comprises a PMOS device 221 (e.g., P-MOSFET)coupled to an HBT device 222 (e.g., GaAs HBT device). In one embodiment,the β varies from 40 to 140 and ηβ≈52 and σβ≈15% for the HBT device 222.The HBT device 222 is coupled to a current source 223 and an amplifier224. The current source 223 generates a reference current I_(ref) (e.g.,20 μA) which is fed into the collector of the HBT device 222, and theamplifier 224 drives the gate of the PMOS device 221.

A common mode voltage V_(cm) (e.g., 1.1 V) is coupled to thenon-inverting (+) input of the amplifier 224. Because little or nocurrent flows into the inverting (−) and non-inverting (+) inputs of theamplifier 224, the input voltages at the inverting (−) and non-inverting(+) inputs are substantially equal, and the voltage at the inverting (−)input of the amplifier 224 and the collector of the HBT device 222 isV_(cm). If the collector of the HBT device 222 is kept at the voltagelevel V_(cm), the HBT device 222 is guaranteed to operate in the linearregion. If not at V_(cm), the amplifier 224 will generate a compensatingvoltage such as a negative pulling voltage if the voltage is too high.

The V_(tune1) generator 230 comprises a transistor 231. In variousembodiments, the transistor 231 may be similar to and closely match thePMOS device 221. The source of the transistor 231 is coupled to thecommon supply voltage V_(DD), and the gate of the transistor 231 isdriven by the output of the amplifier 224. Accordingly, the currentI_(D) driven by the transistor 231 is proportional to 1/β and is equalto I_(ref)/β. In the V_(tune1) generator 230, the drain current I_(D) ismultiplied by a multiplier K₁ 232 to generate a current I_(D1). Themultiplier K₁ 232 may be individually controlled by the serial controlinterface 210.

The V_(tune1) generator 230 comprises an amplifier 233. The output ofthe amplifier 233 is coupled to the gate of a transistor M_(1c) 234, andthe inverting (−) input of the amplifier 233 is coupled to the drain ofthe transistor M_(1c) 234. The common mode voltage V_(cm) is coupled tothe non-inverting (+) input of the amplifier 233 and is coupled to thegate of a transistor M₁ 235. Accordingly, the voltage at the inverting(−) input of the amplifier 233 and the drain of the transistor M_(1c)234 is V_(cm).

The source of the transistor M_(1c) 234 is coupled to the drain of thetransistor M₁ 235 at a node 236. The current I_(D1) is equal to thedrain current in the transistor M_(1c) 234 and is forced into thetransistor M₁ 235 to generate the bias control signal V_(tune1) at thenode 236. The tuning voltage V_(tune1) may be a voltage that keeps thetransistor M₁ 235 in a saturated or final state. In one embodiment, thetransistors M_(1c) 234 and M₁ 235 may comprise N-MOSFET transistorsbiased in triode mode, for example.

The V_(tune2) generator 240 comprises a transistor 241. In variousembodiments, the transistor 241 may be similar to and closely match thePMOS device 221. The source of the transistor 241 is coupled to thecommon supply voltage V_(DD), and the gate of the transistor 241 isdriven by the output of the amplifier 224. Accordingly, the currentI_(D) driven by the transistor 241 is proportional to 1/β and is equalto I_(ref)/β. In the V_(tune2) generator 240, the drain current I_(D) ismultiplied by a multiplier K₂ 242 to generate a current I_(D2). Themultiplier K₂ 242 may be individually controlled by the serial controlinterface 210.

The V_(tune2) generator 240 comprises an amplifier 243. The output ofthe amplifier 243 is coupled to the gate of a transistor M_(2c) 244, andthe inverting (−) input of the amplifier 243 is coupled to the drain ofthe transistor M_(2c) 244. The common mode voltage V_(cm) is coupled tothe non-inverting (+) input of the amplifier 243 and is coupled to thegate of a transistor M₂ 245. Accordingly, the voltage at the inverting(−) input of the amplifier 243 and the drain of the transistor M_(2c)244 is V_(cm).

The source of the transistor M_(2c) 244 is coupled to the drain of thetransistor M₂ 245 at a node 246. The current I_(D2) is equal to thedrain current in the transistor M_(2c) 244 and is forced into thetransistor M₂ 245 to generate the bias control signal V_(tune2) at thenode 246. The tuning voltage V_(tune2) may be a voltage that keeps thetransistor M₂ 245 in a saturated or final state. In one embodiment, thetransistors M_(2c) and M₂ 245 may comprise N-MOSFET transistors biasedin triode mode, for example.

The V_(tune3) generator 250 comprises a transistor 251. In variousembodiments, the transistor 251 may be similar to and closely match thePMOS device 221. The source of the transistor 251 is coupled to thecommon supply voltage V_(DD), and the gate of the transistor 251 isdriven by the output of the amplifier 224. Accordingly, the currentI_(D) driven by the transistor 251 is proportional to 1/β and is equalto I_(ref)/β. In the V_(tune3) generator 250, the drain current I_(D) ismultiplied by a multiplier K₃ 252 to generate a current I_(D3). Themultiplier K₃ 252 may be individually controlled by the serial controlinterface 210.

The V_(tune3) generator 250 comprises an amplifier 253. The output ofthe amplifier 253 is coupled to the gate of a transistor M_(3c) 254, andthe inverting (−) input of the amplifier 253 is coupled to the drain ofthe transistor M_(3c) 254. The common mode voltage V_(cm) is coupled tothe non-inverting (+) input of the amplifier 253 and is coupled to thegate of a transistor M₃ 255. Accordingly, the voltage at the inverting(−) input of the amplifier 253 and the drain of the transistor M_(3c)254 is V_(cm).

The source of the transistor M_(3c) 254 is coupled to the drain of thetransistor M₃ 255 at a node 256. The current I_(D3) is equal to thedrain current in the transistor M_(3c) 254 and is forced into thetransistor M₃ 255 to generate the bias control signal V_(tune3) at thenode 256 through an amplifier 257. The tuning voltage V_(tune3) may be avoltage that keeps the transistor M₃ 255 in a saturated or final state.In one embodiment, the transistors M_(3c) 254 and M₃ 255 may compriseN-MOSFET transistors biased in triode mode, for example.

FIG. 3 illustrates one embodiment of an output driver system 300. Invarious embodiments, the output driver system 300 may be implemented bythe baseband processor 120 depicted in FIG. 1. The embodiments, however,are not limited in this context.

The output driver system 300 may comprise a plurality of output driversincluding G_(m3) drivers 310-1-n, where n may be equal to any positiveinteger value (e.g., n=11). As shown, some of the output drivers such asoutput drivers 310-1-4 (e.g., x1, x2, x4, and x8) may be binaryweighted, and some of the output drivers 310-5-n may be weighted equally(e.g., xN). In one embodiment, for example, xN may be equal to x16. Theembodiments, however, are not limited in this context.

In various embodiments, the tuning voltage V_(tune3) may be provided tothe G_(m3) drivers 310-1-n to adjust and control the G_(m3) value toprovide optimized RF PA power efficiency over a range of output power.Each of the G_(m3) drivers 310-1-n may comprise, for example, amultiplier for multiplying the tuning voltage V_(tune3). In variousimplementations, the value G_(m3) may be adjusted to provide a constantratio among the G_(m3) output drivers 310-1-n and other output drivers(e.g., a G_(m1) driver and a G_(m2) driver). By adjusting the valueG_(m3), the amount by which the base currents I_(b1)-I_(bN) _(—) _(n)are adjusted may be controlled.

As shown, the G_(m3) drivers 310-1-n may be adjusted by a certain amountaccording to the power level. In various embodiments, the G_(m3) drivers310-1-n may be arranged to use a single power level signal tosimultaneously adjust the base currents I_(b1)-I_(bN) _(—) _(n). In suchembodiments, the power level may be filtered by a bank of filters, forexample, and sent to the G_(m3) drivers 310-1-n.

In some implementations, the power level may comprise, a single powercontrol voltage applied to the G_(m3) drivers 310-1-n as well as toother drivers (e.g., a G_(m1) driver and a G_(m2) driver). In suchimplementations, unified or “single point” power control is provided forestablishing the output power of an RF PA.

In various embodiments, the G_(m3) drivers 310-1-n may be biased tocompensate for variations in on-chip and off-chip device parameters,such as CMOS process variations, power supply variations, temperaturevariations, G_(m) variations, and so forth. For example, the G drivers310-1-n may generate base currents I_(b1)-I_(bN) _(—) _(n) based on asignal proportional to 1/β.

In effect, the combined base currents I_(b1)-I_(bN) _(—) _(n) form anamplitude signal comprising an n-bit digital word (e.g., 11-bit digitalword). In various embodiments, each bit of the n-bit digital word maycorrespond to a switching transistor in an RFDAC gain stage. Eachswitching transistor may be biased ON or OFF depending on thecorresponding bit value. By biasing certain switching transistors ON andOFF, the combined base currents I_(b1)-I_(bN) _(—) _(n) may be used toeffectively control the amplification provided by the RFDAC gain stage.

FIG. 4 illustrates one embodiment of an RFDAC 400. In variousembodiments, the RFDAC 400 may comprise or be implemented as the RFDAC110 depicted in FIG. 1. The embodiments, however, are not limited inthis context.

As shown, the RFDAC 400 may comprise a plurality of gain stagesincluding a first gain stage 410, a second gain stage 420, and a thirdgain stage 430 which may be AC coupled together. In this embodiment, thefirst gain stage 410 comprises a coupling capacitor 411 and a transistor412 having an inductor 413 as a load. The second gain stage 420comprises a coupling 421 capacitor and a transistor 422 having aninductor 423 as a load. The inductors 413, 423 may be used to amplify ACbut not DC signals.

In this embodiment, the third gain stage 430 comprises a couplingcapacitor 431 and a plurality of switching transistors 432-1-n, where nmay represent any positive integer value (e.g., n=11). The third gainstage 430 also comprises a plurality of resistors 433-1-n and aplurality of capacitors 434-1-n coupled to the bases of the switchingtransistors 432-1-n. As shown, some transistors such as switchingtransistors 432-1-4 (e.g., x1, x2, x4, and x8) may be binary weighted,and some transistors such as switching transistors 432-5-n may beweighted equally (e.g., xN). In one embodiment, for example, xN may beequal to x16. The embodiments, however, are not limited in this context.

In various implementations, an RF signal Φ and a base current I_(B1) areapplied to the first gain stage 410 of the RFDAC 200. In the first gainstage 410, the input RF signal Φ is applied to the capacitor 411, andthe base current I_(B1) is applied to the base of the transistor 412. Assuch, the transistor 412 is biased by the base current I_(B1) and ismodulated by the RF signal Φ.

In the second gain stage 420, a base current I_(B2) is applied to thebase of transistor 422. The transistor 422 is biased by the base currentI_(B2) and is modulated by the RF signal that was amplified by the firstgain stage 410. In general, the base current I_(B1) and the base currentI_(B2) will be different because the second gain stage 420 is amplifiedby the first gain stage 410. Therefore, the second gain stage 420 isbiased at a higher DC output point.

After being amplified by the first gain stage 410 and the second gainstage 420, the amplified RF signal Φ is sent to the third gain stage430. In the third gain stage 430, the amplified RF signal Φ is modulatedby a baseband signal and is then transmitted through the antenna 435. Inthis embodiment, the baseband signal may comprise an amplitude signalprovided to the third gain stage 430 through base currents I_(b1)-I_(bN)_(—) _(n). In effect, the combined base currents I_(b1)-I_(bN) _(—) _(n)form an amplitude signal comprising an n-bit digital word (e.g., 11-bitdigital word). Each bit of the n-bit digital word corresponds to one ofthe switching transistors 432-1-n, and each one of the switchingtransistors 432-1-n is biased ON or OFF depending on the correspondingbit value. By biasing certain switching transistors ON and OFF, theamplification of the RF signal Φ provided by the third gain stage 430may be effectively controlled.

As shown, the RFDAC 400 may comprise a sense device 436 implemented anHBT device formed integrally on the same substrate as the othertransistors of the RFDAC 400 so that the variations due to processvariables for the other transistors of the RFDAC 400 and the sensedevice 436 are similar. In various implementations, a current MV_B maybe received at the base of the sense device 436 and a fixed precisioncurrent MV_C may be received at the collector of the sense device 436for determining the β of the sense device 436.

Numerous specific details have been set forth herein to provide athorough understanding of the embodiments. It will be understood bythose skilled in the art, however, that the embodiments may be practicedwithout these specific details. In other instances, well-knownoperations, components and circuits have not been described in detail soas not to obscure the embodiments. It can be appreciated that thespecific structural and functional details disclosed herein may berepresentative and do not necessarily limit the scope of theembodiments.

It is also worthy to note that any reference to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment. The appearances of the phrase “in oneembodiment” in various places in the specification are not necessarilyall referring to the same embodiment.

Some embodiments may be implemented using an architecture that may varyin accordance with any number of factors, such as desired computationalrate, power levels, heat tolerances, processing cycle budget, input datarates, output data rates, memory resources, data bus speeds and otherperformance constraints. The embodiments are not limited in thiscontext.

While certain features of the embodiments have been illustrated asdescribed herein, many modifications, substitutions, changes andequivalents will now occur to those skilled in the art. It is thereforeto be understood that the appended claims are intended to cover all suchmodifications and changes as fall within the true spirit of theembodiments.

1. A baseband processor comprising: a plurality of output drivers togenerate a plurality of base currents for biasing a radio frequencydigital-to-analog converter; a serial control interface to generate aprogramming signal for controlling a relationship among said pluralityof base currents, and a plurality of tuning voltage generators togenerate a plurality of tuning voltages for biasing said plurality ofoutput drivers, each of said plurality of tuning voltage generatorscomprising a current multiplier to be programmed by said serial controlinterface.
 2. The baseband processor of claim 1, said relationshipcomprising a fixed ratio among said plurality of base currents. 3.(canceled)
 4. (canceled)
 5. A baseband processor, comprising: aplurality of output drivers to generate a plurality of base currents forbiasing a radio frequency digital-to-analog converter, a serial controlinterface to generate a programming signal for controlling arelationship among said plurality of base currents; and a plurality oftuning voltage generators to generate a plurality of tuning voltages forbiasing said plurality of output drivers said serial control interfaceto control a ratio among said plurality of tuning voltages.
 6. Abaseband processor, comprising: a plurality of output drivers togenerate a plurality of base currents for biasing a radio frequencydigital-to-analog converter, a serial control interface to generate aprogramming signal for controlling a relationship among said pluralityof base currents; and a plurality of tuning voltage generators togenerate a plurality of tuning voltages for biasing said plurality ofoutput drivers said plurality of tuning voltage generators to adjusttransconductance values of said plurality of output drivers.
 7. Thebaseband processor of claim 1, said plurality of output drivers toreceive a single power level signal to adjust said plurality of basecurrents.
 8. The baseband processor of claim 7, said power level signalcomprising a single power control voltage.
 9. A baseband processorcomprising a plurality of output drivers to generate a plurality of basecurrents for biasing a radio frequency digital-to-analog converter saidplurality of output drivers to receive a single power level signal toadjust said plurality of base currents; a serial control interface togenerate a programming signal for controlling a relationship among saidplurality of base currents; and one or more analog multiplexers toreceive said single power level signal.
 10. The baseband processor ofclaim 9, said one or more analog multiplexers to receive an amplitudesignal and to scale said amplitude signal according to said single powerlevel signal.
 11. A baseband processor of claim 7, further comprising: aplurality of output drivers to generate a plurality of base currents forbiasing a radio frequency digital-to-analog converter said plurality ofoutput drivers to receive a single power level signal to adjust saidplurality of base currents; a serial control interface to generate aprogramming signal for controlling a relationship among said pluralityof base currents; and one or more filters to provide said single powerlevel signal to said plurality of output drivers.
 12. A basebandprocessor of comprising: a plurality of output drivers to generate aplurality of base currents for biasing a radio frequencydigital-to-analog converter; and a serial control interface to generatea programming signal for controlling a relationship among said pluralityof base currents, said baseband processor to detect a current gain (β)of said radio frequency digital-to-analog converter and to generate acompensation signal proportional to 1/β.
 13. The baseband processor ofclaim 12, further comprising a plurality of voltage tuning generators togenerate a plurality of tuning voltages based on said compensationsignal.
 14. The baseband processor of claim 1, said radio frequencydigital-to-analog converter comprising a plurality of gain stages to bebiased by said plurality of base currents. 15-20. (canceled)
 21. Thebaseband processor of claim 5, said plurality of output drivers toreceive a single power level signal to adjust said plurality of basecurrents.
 22. The baseband processor of claim 21, said power levelsignal comprising a single power control voltage.
 23. The basebandprocessor of claim 5, said radio frequency digital-to-analog convertercomprising a plurality of gain stages to be biased by said plurality ofbase currents.
 24. The baseband processor of claim 6, said plurality ofoutput drivers to receive a single power level signal to adjust saidplurality of base currents.
 25. The baseband processor of claim 24, saidpower level signal comprising a single power control voltage.
 26. Thebaseband processor of claim 6, said radio frequency digital-to-analogconverter comprising a plurality of gain stages to be biased by saidplurality of base currents.
 27. The baseband processor of claim 9, saidpower level signal comprising a single power control voltage.
 28. Thebaseband processor of claim 9, said radio frequency digital-to-analogconverter comprising a plurality of gain stages to be biased by saidplurality of base currents.
 29. The baseband processor of claim 11, saidpower level signal comprising a single power control voltage.
 30. Thebaseband processor of claim 11, said radio frequency digital-to-analogconverter comprising a plurality of gain stages to be biased by saidplurality of base currents.